1. Technical Field
The present invention relates to semiconductor wafers, and more particularly to wafers and methods for reducing backside wafer defects.
2. Description of the Related Art
During standard semiconductor wafer processing, a backside of a silicon wafer incurs defects that cannot be eliminated with traditional surface cleaning processes. Defects can include both additions to the backside as well as micro-gouging in the exposed substrate surface. While such defects may not pose a concern to whole-wafer fabrication processing or to the performance of devices and other front-side features, once the wafers are converted to chips and assembled in standard bond and assembly packaging processing, significant issues with chip cracking have been observed due to backside defects which serve as stress concentrators or initiation locations for microcracks.
These defects may be difficult or impossible to easily detect reliably in-line. Even if detected during wafer fabrication, limitations with traditional wet chemistries designed to clean or etch silicon pose challenges to remedying backside defects with processes and methods that are typically compatible with back-end-of-line (BEOL) semiconductor processing. Such processes usually blunt cracks without removing them and possibly induce additional defects as artifacts of the backside clean processing.
While some silicon etchants known in the art may successfully remove some micro-cracks, different types of defects such as pitting may still occur on the wafer backside as a result of the backside etch processing. Such defects have been observed even on wafer backsides which have been terminated with a chemical mechanical polish (CMP) which gives a planar surface with a mirrored finish. Further, the use of a backside wet etch increases variability in outgoing wafer thickness, which increases variability in downstream processing and creates challenges with automated wafer handling. Higher variability leads to the need for increased inspections and rework, thus resulting in longer wafer fabrication time and increased cost per wafer. Additionally, the inscribed wafer identifier (ID) can also be damaged or obscured by a non-selective silicon wet thinning operation, which poses a significant challenge for automated wafer handling.
Backside defects can be a customer satisfaction issue. Degraded strength of the chip due to backside defects has been shown to correlate with module build yield and potential in-field reliability issues. In addition to aesthetic issues which confound in-line inspection data and lead to issues with supplier rejection, the defects induced by the wet silicon etch may cause pitting in the wafer backside surface, which poses a longer term reliability concern with chip cracking, which also may negatively impact customer satisfaction.